1. Field of the Invention
The present invention relates generally to semiconductor chip packages, and more particularly, to methods for manufacturing chip-size packages at a wafer-level and the resulting chip-size package structures.
2. Description of the Related Art
The major trend in the electronics industry today is to make products lighter, smaller, faster, more multi-functional, more powerful, more reliable, and less expensive. One of the key technologies to make these product design goals possible is electronic packaging and assembly technology.
One particular packaging technology, chip-size or chip-scale packaging (CSP), has many advantages compared to conventional packaging such as quad flat packaging (QFP), ball grid array (BGA), and the like. The most obvious advantage is the size of the package, that is, the package is the same size as the chip or slightly larger. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die (KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and reworkability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path. Further background information is available in "Chip-Size Packaging Developments", August 1995, TechSearch International, Inc.
However, CSP has at least one disadvantage compared to conventional SMT and flip chip technology, namely, high cost per unit. However, this problem could be eliminated if chip-sized packages could be mass produced more easily.
In many cases, the connections between circuit boards and CSP devices are accomplished using metallic bumps. One of the limitations of many CSP production methods is the need for flexibility in the number, arrangement, and size of metallic bumps that can be disposed on a CSP device.
A need exists therefore, for a CSP device that allows for flexible arrangement of metallic bumps and that can be mass produced at the wafer level.